Edukad projektid

eesti keeles / in English

Verification and Validation of Embedded System Design Workbench that is how to make sure that systems controlled by intelligent electronic chips will satisfy certain safety conditions

acronym: VERTIGO
start: 2006-06-01
end: 2008-11-30
programme: FP6 - Euroopa Liidu 6. raamprogramm
sub-programme: IST - Infoühiskonna tehnoloogiad
instrument: STREP - Sihtotstarbelised teadusprojektid
call identifier: FP6-2005-IST-5
project number: 033709
duration in months: 30
partner count: 8
partner no and role partner name country contact person web page
1 coordinator STMICROELECTRONICS S.R.L. IT Umberto Rossi
7 partner Tallinna Tehnikaülikool EE